Datasheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
MC9S12E128 Data Sheet, Rev. 1.07
514 Freescale Semiconductor
Figure 18-1. MEBI Block Diagram
PE[7:2]/NOACC/
PE1/
IRQ
PE0/XIRQ
BKGD/MODC/TAGHI
PK[7:0]/ECS/XCS/X[19:14]
PA[7:0]/A[15:8]/
D[15:8]/D[7:0]
Port KPort A
PB[7:0]/A[7:0]/
D[7:0]
Port BPort E
BKGD
REGS
EXT
BUS
I/F
CTL
Addr[19:0]
Data[15:0]
(Control)
Internal Bus
ECLK CTL
IRQ CTL
ADDR
ADDR
DATA
ADDR
DATA
PIPE CTL
CPU pipe info
IRQ interrupt
XIRQ interrupt
BDM tag info
IPIPE1/MODB/CLKTO
IPIPE0/MODA/
ECLK/
LSTRB/TAGLO
R/W
TAG CTL
Control signal(s)
Data signal (unidirectional)
Data bus (unidirectional)
Data bus (bidirectional)
Data signal (bidirectional)
mode