Datasheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
MC9S12E128 Data Sheet, Rev. 1.07
518 Freescale Semiconductor
18.3 Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Table 18-2. Detailed
descriptions of the registers and bits are given in the subsections that follow. On most chips the registers
are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
18.3.1 Module Memory Map
Table 18-2. MEBI Memory Map
Address
Offset
Use Access
0x0000 Port A Data Register (PORTA) R/W
0x0001 Port B Data Register (PORTB) R/W
0x0002 Data Direction Register A (DDRA) R/W
0x0003 Data Direction Register B (DDRB) R/W
0x0004 Reserved R
0x0005 Reserved R
0x0006 Reserved R
0x0007 Reserved R
0x0008 Port E Data Register (PORTE) R/W
0x0009 Data Direction Register E (DDRE) R/W
0x000A Port E Assignment Register (PEAR) R/W
0x000B Mode Register (MODE) R/W
0x000C Pull Control Register (PUCR) R/W
0x000D Reduced Drive Register (RDRIV) R/W
0x000E External Bus Interface Control Register (EBICTL) R/W
0x000F Reserved R
0x001E IRQ Control Register (IRQCR) R/W
0x00032 Port K Data Register (PORTK) R/W
0x00033 Data Direction Register K (DDRK) R/W