Datasheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)

MC9S12E128 Data Sheet, Rev. 1.07

522 Freescale Semiconductor

18.3.2.4 Data Direction Register B (DDRB)

Read: Anytime when register is in the map

Write: Anytime when register is in the map

This register controls the data direction for port B. When port B is operating as a general-purpose I/O port,

DDRB determines the primary direction for each port B pin. A 1 causes the associated port pin to be an

output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects

the source of data for reads of the corresponding PORTB register. If the DDR bit is 0 (input) the buffered

pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read.

This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these

accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control

signals.

76543210

Bit 7 6 5 4321Bit 0

Reset 0 0 0 00000

Figure 18-5. Data Direction Register B (DDRB)

Table 18-4. DDRB Field Descriptions

Field Description

7:0

DDRB

Data Direction Port B

0 Conﬁgure the corresponding I/O pin as an input

1 Conﬁgure the corresponding I/O pin as an output