Datasheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 527
Table 18-6. PEAR Field Descriptions
Field Description
7
NOACCE
CPU No Access Output Enable
Normal: write once
Emulation: write never
Special: write anytime
1 The associated pin (port E, bit 7) is general-purpose I/O.
0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle.
This bit has no effect in single-chip or special peripheral modes.
5
PIPOE
Pipe Status Signal Output Enable
Normal: write once
Emulation: write never
Special: write anytime.
0 The associated pins (port E, bits 6:5) are general-purpose I/O.
1 The associated pins (port E, bits 6:5) are outputs and indicate the state of the instruction queue
This bit has no effect in single-chip or special peripheral modes.
4
NECLK
No External E Clock
Normal and special: write anytime
Emulation: write never
0 The associated pin (port E, bit 4) is the external E clock pin. External E clock is free-running if ESTR = 0
1 The associated pin (port E, bit 4) is a general-purpose I/O pin.
External E clock is available as an output in all modes.
3
LSTRE
Low Strobe (
LSTRB) Enable
Normal: write once
Emulation: write never
Special: write anytime.
0 The associated pin (port E, bit 3) is a general-purpose I/O pin.
1 The associated pin (port E, bit 3) is configured as the
LSTRB bus control output. If BDM tagging is enabled,
TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK.
This bit has no effect in single-chip, peripheral, or normal expanded narrow modes.
Note:
LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled to provide
an extra I/O pin. If
LSTRB is needed, it should be enabled before any external writes. External reads do
not normally need
LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of
data.
2
RDWE
Read/Write Enable
Normal: write once
Emulation: write never
Special: write anytime
0 The associated pin (port E, bit 2) is a general-purpose I/O pin.
1 The associated pin (port E, bit 2) is configured as the R/
W pin
This bit has no effect in single-chip or special peripheral modes.
Note: R/
W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra
I/O pin. If R/
W is needed it should be enabled before any external writes.