Datasheet

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 533
18.3.2.13 Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to
this register have no effect.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
18.3.2.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below
Write: See individual bit descriptions below
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 18-17. Reserved Register
76543210
R
IRQE IRQEN
000000
W
Reset 01000000
= Unimplemented or Reserved
Figure 18-18. IRQ Control Register (IRQCR)
Table 18-12. IRQCR Field Descriptions
Field Description
7
IRQE
IRQ Select Edge Sensitive Only
Special modes: read or write anytime
Normal and Emulation modes: read anytime, write once
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
6
IRQEN
External IRQ Enable
Normal, emulation, and special modes: read or write anytime
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
Note: When IRQEN = 0, the edge detect latch is disabled.