Datasheet

MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 543
Chapter 19
Module Mapping Control (MMCV4)
19.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core
platform.
The block diagram of the MMC is shown in Figure 19-1.
Figure 19-1. MMC Block Diagram
The MMC is the sub-module which controls memory map assignment and selection of internal resources
and external space. Internal buses between the core and memories and between the core and peripherals is
controlled in this module. The memory expansion is generated in this module.
MMC
MODE INFORMATION
REGISTERS
CPU WRITE DATA BUS
CPU ADDRESS BUS
CPU CONTROL
STOP, WAIT
ADDRESS DECODE
CPU READ DATA BUS
EBI ALTERNATE ADDRESS BUS
EBI ALTERNATE WRITE DATA BUS
EBI ALTERNATE READ DATA BUS
SECURITY
CLOCKS, RESET
READ & WRITE ENABLES
ALTERNATE ADDRESS BUS (BDM)
ALTERNATE WRITE DATA BUS (BDM)
ALTERNATE READ DATA BUS (BDM)
CORE SELECT (S)
PORT K INTERFACE
MEMORY SPACE SELECT(S)
PERIPHERAL SELECT
BUS CONTROL
SECURE
BDM_UNSECURE
MMC_SECURE
INTERNAL MEMORY
EXPANSION