Datasheet

Chapter 19 Module Mapping Control (MMCV4)
MC9S12E128 Data Sheet, Rev. 1.07
554 Freescale Semiconductor
NOTE
As stated, the bits in this register provide read visibility to the system
memory space and on-chip/off-chip partitioning allocations defined at
system integration. The actual array size for any given type of memory
block may differ from the allocated size. Please refer to the device overview
chapter for actual sizes.
19.3.2.9 Program Page Index Register (PPAGE)
Read: Anytime
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see device overview chapter.
Table 19-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0
Allocated FLASH
or ROM Space
00 0K byte
01 16K bytes
10 48K bytes
(1)
11 64K bytes
(1)
NOTES:
1. The ROMHM software bit in the MISC register determines the accessibility of the
FLASH/ROM memory space. Please refer to Section 19.3.2.8, “Memory Size Register
1 (MEMSIZ1),” for a detailed functional description of the ROMHM bit.
Table 19-12. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 Off-Chip Space On-Chip Space
00 876K bytes 128K bytes
01 768K bytes 256K bytes
10 512K bytes 512K bytes
11 0K byte 1M byte
76543210
R0 0
PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
W
Reset
1
————————
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
actual reset state of this register.
= Unimplemented or Reserved
Figure 19-11. Program Page Index Register (PPAGE)