Datasheet

Appendix A Electrical Characteristics
MC9S12E128 Data Sheet, Rev. 1.07
574 Freescale Semiconductor
A.3 Startup, Oscillator and PLL
A.3.1 Startup
Table A-11 summarizes several startup characteristics explained in this section.
A.3.1.1 POR
The release level V
PORR
and the assert level V
PORA
are derived from the V
DD
Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.3.1.2 LVR
The release level V
LVRR
and the assert level V
LVRA
are derived from the V
DD
Supply. They are also valid
if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check
are started. If after a time t
CQOUT
no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n
uposc
.
A.3.1.3 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
Table A-11. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C Rating Symbol Min Typ Max Unit
1 T POR release level
V
PORR
2.07 V
2 T POR assert level
V
PORA
0.97 V
3 D Reset input pulse width, minimum input time
PW
RSTL
2
t
osc
4 D Startup from Reset
n
RST
192 196
n
osc
5D
Interrupt pulse width,
IRQ edge-sensitive
mode
PW
IRQ
20 ns
6 D Wait recovery startup time
t
WRS
14
t
cyc
7 P LVR release level
V
LVRR
2.25 V
8 P LVR assert level
V
LVRA
2.55 V