Datasheet

Appendix A Electrical Characteristics
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 587
A.5.2 Slave Mode
In Figure A-6 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
Figure A-6. SPI Slave Timing (CPHA = 0)
In Figure A-7 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
Figure A-7. SPI Slave Timing (CPHA = 1)
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
SS
(INPUT)
1
9
5 6
MSB IN
BIT 6 . . . 1
LSB IN
SLAVE MSB
SLAVE LSB OUT
BIT 6 . . . 1
11
4
4
2
7
(CPOL = 0)
(CPOL = 1)
3
13
NOTE: Not defined!
12
12
11
SEE
13
NOTE
8
10
see
note
SCK
(INPUT)
SCK
(INPUT)
MOSI
(INPUT)
MISO
(OUTPUT)
1
5 6
MSB IN
BIT 6 . . . 1
LSB IN
MSB OUT SLAVE LSB OUT
BIT 6 . . . 1
4
4
9
12 13
11
(CPOL = 0)
(CPOL = 1)
SS
(INPUT)
2
12 13
3
NOTE: Not defined!
SLAVE
7
8
see
note