Datasheet
Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
MC9S12E128 Data Sheet, Rev. 1.07
62 Freescale Semiconductor
1.3.2 Signal Properties Summary
Table 1-4. Signal Properties
Pin Name
Function 1
Pin Name
Function 2
Pin Name
Function 3
Power
Domain
Internal Pull Resistor
Description
CTRL Reset State
EXTAL — — VDDPLL NA NA Oscillator pins
XTAL — — VDDPLL NA NA
XFC — — VDDPLL NA NA PLL loop filter pin
RESET — — VDDX None None External reset pin
BKGD MODC TAGHI VDDX Up Up Background debug, mode pin, tag signal
high
TEST VPP — NA NA NA Test pin only
PAD[15,13,
12,8,6,4,2,0]
AN[15,13,
12,8,6,4,2,0]
KWAD[15,13,
12,8,6,4,2,0]
VDDX PERAD/
PPSAD
Disabled Port AD I/O Pins, ATD inputs, keypad
Wake-up
PAD[14,11,
10,9,7,5,3,1]
AN[14,11,
10,9,7,5,3,1]
KWAD[14,11,
10,9,7,5,3,1]
VDDX PERAD/
PPSAD
Disabled Port AD I/O Pins, ATD inputs, keypad
Wake-up
PA[7:0] ADDR[15:8]/
DATA[15:8]
— VDDX PUCR Disabled Port A I/O pin, multiplexed
address/data
PB[7:0] ADDR[7:0]/
DATA[7:0]
— VDDX PUCR Disabled Port B I/O pin, multiplexed
address/data
PE7 NOACC XCLKS VDDX Input Input Port E I/O pin, access, clock select
PE6 IPIPE1 MODB VDDX While
RESET is low:
Down
Port E I/O pin, pipe status, mode
selection
PE5 IPIPE0 MODA VDDX While
RESET is low:
Down
Port E I/O pin, pipe status, mode
selection
PE4 ECLK — VDDX PUCR Mode Dep
1
Port E I/O pin, bus clock output
PE3
LSTRB TAGLO VDDX PUCR Mode Dep
1
Port E I/O pin, low strobe, tag signal
low
PE2 R/
W — VDDX PUCR Mode Dep
1
Port E I/O pin, R/W in expanded modes
PE1 IRQ — VDDX PUCR Up Port E input, external interrupt pin
PE0 XIRQ — VDDX PUCR Up Port E input, non-maskable interrupt pin
PK[7] ECS ROMCTL VDDX PUCR Up Port K I/O Pin, Emulation Chip Select
PK[6] XCS — VDDX PUCR Up Port K I/O Pin, External Chip Select
PK[5:0] XADDR[19:14] — VDDX PUCR Up Port K I/O Pins, Extended Addresses
PM7 SCL — VDDX PERM/
PPSM
Up Port M I/O Pin, IIC SCL signal
PM6 SDA — VDDX PERM/
PPSM
Up Port M I/O Pin, IIC SDA signal
PM5 TXD2 — VDDX PERM/
PPSM
Up Port M I/O Pin, SCI2 transmit signal
PM4 RXD2 — VDDX PERM/
PPSM
Up Port M I/O Pin, SCI2 receive signal
PM3 — — VDDX PERM/
PPSM
Disabled Port M I/O Pin
PM1 DAO1 — VDDX PERM/
PPSM
Disabled Port M I/O Pin, DAC1 output