Datasheet

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 65
1.4.8 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free cycle”. This signal
will assert when the CPU is not using the bus. The
XCLKS is an input signal which controls whether a
crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce
oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of
RESET. If
the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If
the input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is
an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts
oscillator circuit on EXTAL and XTAL.
Figure 1-8. Colpitts Oscillator Connections (PE7 = 1)
Figure 1-9. Pierce Oscillator Connections (PE7 = 0)
1.4.9 PE6 / MODB / IPIPE1 — Port E I/O Pin 6
PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the
instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active
when RESET is low. PE6 is not available in the 80 pin package version.
MCU
C2
EXTAL
XTAL
Crystal or
VSSPLL
ceramic resonator
C1
CDC
1
1. Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is
applied to the crystal. Please contact the crystal manufacturer for crystal DC
MCU
EXTAL
XTAL
RS
1
RB
VSSPLL
Crystal or
ceramic resonator
C2
C1
1. Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.