Datasheet

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
MC9S12E128 Data Sheet, Rev. 1.07
74 Freescale Semiconductor
1.5 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG block description
chapter for details on clock generation.
Figure 1-10. Clock Connections
Table 1-6. Clock Selection Based on PE7
PE7 = XCLKS Description
1 Colpitts Oscillator selected
0 Pierce Oscillator/external clock selected
CRG
Bus Clock
Core Clock
EXTAL
XTAL
Oscillator Clock
HCS12 CORE
PWM
RAM
PIM
IIC
DAC
Flash
ATD
SCI0, SCI1, SCI2
PMF
SPI
BDM
OSC
CPU
MEBI MMC
INT DBG
TIM0, TIM1, TIM2
VREG