Datasheet

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 75
1.6 Modes of Operation
1.6.1 Overview
Eight possible modes determine the operating configuration of the MC9S12E128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.6.2 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the HCS12 MEBI block description chapter.
Table 1-7. Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
Mode Description
0 0 0 X 1 Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
00101Emulation Expanded Narrow, BDM allowed
10
0 1 0 X 0 Special Test (Expanded Wide), BDM allowed
01101Emulation Expanded Wide, BDM allowed
10
1 0 0 X 1 Normal Single Chip, BDM allowed
10100Normal Expanded Narrow, BDM allowed
11
1 1 0 X 1 Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
11100Normal Expanded Wide, BDM allowed
11
Table 1-8. Clock Selection Based on PE7
PE7 = XCLKS
Description
1 Colpitts Oscillator selected
0 Pierce Oscillator/external clock selected