Datasheet

Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor 91
2.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
2.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence,
indicated by F in Figure 2-5.
Module Base + 0x0000
76543210
R FDIVLD
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
Table 2-3. FCLKDIV Field Descriptions
Field Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written to since the last reset
6
PRDIV8
Enable Prescalar by 8
0 The oscillator clock is directly fed into the Flash clock divider
1 The oscillator clock is divided by 8 before feeding into the Flash clock divider
5–0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to Section 2.4.1.1, “Writing the
FCLKDIV Register” for more information.
Module Base + 0x0001
76543210
R KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0
W
Reset F F FFFFFF
= Unimplemented or Reserved
Figure 2-5. Flash Security Register (FSEC)