Datasheet

24.0.7 Ports
24.0.7.1 BKGD Pin
The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the
BKGD pin is used as MODC input.
24.0.7.2 Port A and B
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O.
24.0.7.3 Port E
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2
output running at the core clock rate. The clock output is always enabled in emulation modes.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK
output running at the bus clock rate or at the programmed divided clock rate. The clock output is
always enabled in emulation modes.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-
sensitive
IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit
(Section 24.0.5.10, “IRQ Control Register (IRQCR)”) and clearing the I-bit in the CPU’s condition
code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-
up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive
XIRQ
interrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It
is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.
24.0.7.4 Port K
Port K pins PK[7:0] can be used for either general-purpose I/O.
Table 24-61. Module Implementations on Derivatives
Number
of Modules
MSCAN Modules SPI Modules
CAN0 CAN1 CAN2 CAN3 CAN4 SPI0 SPI1 SPI2
5 yes yes yes yes yes — — —
4 yes yes yes — yes — — —
3 yes yes — — yes yes yes yes
2 yes — — — yes yes yes —
1 yes————yes——