Datasheet

Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
MC9S12XDP512 Data Sheet, Rev. 2.21
1128 Freescale Semiconductor
Figure 27-24. Determination Procedure for PRDIV8 and FDIV Bits
PRDIV8=1
yes
no
PRDIV8=0 (reset)
12.8MHz?
FCLK=(PRDCLK)/(1+FDIV[5:0])
PRDCLK=oscillator_clock
PRDCLK=oscillator_clock/8
PRDCLK[MHz]*(5+Tbus[µs])
no
FDIV[5:0]=PRDCLK[MHz]*(5+Tbus[µs])-1
yes
START
Tbus < 1µs?
an integer?
FDIV[5:0]=INT(PRDCLK[MHz]*(5+Tbus[µs]))
1/FCLK[MHz] + Tbus[µs] > 5
AND
FCLK > 0.15MHz
?
END
yes
no
FDIV[5:0] > 4?
ALL COMMANDS IMPOSSIBLE
yes
no
ALL COMMANDS IMPOSSIBLE
no
TRY TO DECREASE Tbus
yes
oscillator_clock