Datasheet

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
162 Freescale Semiconductor
5.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD.
5.3.1 Module Memory Map
Figure 5-2 gives an overview of all ATD registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
5.3.2 Register Descriptions
This section describes in address order all the ATD registers and their individual bits.
Register
Name
Bit 7 654321Bit 0
ATDCTL0 R 00000
WRAP2 WRAP1 WRAP0
W
ATDCTL1 R
ETRIGSEL
0000
ETRIGCH2 ETRIGCH1 ETRIGCH0
W
ATDCTL2 R
ADPU AFFC AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
W
ATDCTL3 R 0
S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
ATDCTL4 R
SRES8 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
W
ATDCTL5 R
DJM DSGN SCAN MULT
0
CC CB CA
W
ATDSTAT0 R
SCF
0
ETORF FIFOR
0 CC2 CC1 CC0
W
Unimplemente
d
R
W
ATDTEST0 R UUUUUUUU
W
ATDTEST1 R U U 00000
SC
W
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 1 of 5)