Datasheet

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
178 Freescale Semiconductor
5.3.2.11 ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
5.3.2.12 Port Data Register (PORTAD)
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
76543210
R
IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0
W
Reset 00000000
Figure 5-13. ATD Input Enable Register (ATDDIEN)
Table 5-21. ATDDIEN Field Descriptions
Field Description
7–0
IEN[7:0]
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
76543210
R PTAD7 PTAD6 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
W
Reset 11111111
Pin
Function
AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
= Unimplemented or Reserved
Figure 5-14. Port Data Register (PORTAD)
Table 5-22. PORTAD Field Descriptions
Field Description
7–0
PTAD[7:0]
A/D Channel x (ANx) Digital Input (x = 7, 6, 5, 4, 3, 2, 1, 0) — If the digital input buffer on the ANx pin is enabled
(IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1,ETRIGCH[2–0] = x,ETRIGSEL = 0) read
returns the logic level on ANx pin (signal potentials not meeting V
IL
or V
IH
specifications will have an
indeterminate value).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.