Datasheet

Chapter 1 Device Overview MC9S12XD-Family
MC9S12XDP512 Data Sheet, Rev. 2.21
36 Freescale Semiconductor
Figure 1-2. Block Diagram Maskset M42E
128-Kbyte Flash
12 Kbyte RAM
Enhanced Capture
RESET
EXTAL
XTAL
SCI0
2-Kbyte EEPROM
BKGD
XIRQ
ECLKX2/
XCLKS
CPU12X
Periodic Interrupt
COP Watchdog
Clock Monitor
Breakpoints
PLL
V
SSPLL
XFC
V
DDPLL
IRQ
ECLK
PA4
PA3
PA2
PA1
PA0
PA7
PA6
PA5
TEST
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
PE3
PE4
PE5
PE6
PE7
PE0
PE1
PE2
IOC2
IOC6
IOC0
IOC7
IOC1
IOC3
IOC4
IOC5
PT3
PT4
PT5
PT6
PT7
PT0
PT1
PT2
RXD
TXD
MISO
MOSI
PS3
PS4
PS5
PS0
PS1
PS2
SCI1
RXD
TXD
PP3
PP4
PP5
PP6
PP7
PP0
PP1
PP2
SCK
SS
PS6
PS7
SPI0
IIC0
SDA
SCL
CAN0
RXCAN
TXCAN
PM1
PM0
PM2
PM3
PM4
PM5
PM6
PM7
KWH2
KWH6
KWH0
KWH7
KWH1
KWH3
KWH4
KWH5
PH3
PH4
PH5
PH6
PH7
PH0
PH1
PH2
KWJ0
KWJ1
PJ0
PJ1
DDRADDRB
PTAPTB
DDRE
PTE
PTT
DDRT
PTP
DDRP
PTS
DDRS
PTM
DDRM
PTH
DDRH
PTJ
DDRJ
V
DDR
V
SSR
Voltage Regulator 3-5 V
MISO
MOSI
SCK
SS
SPI1
KWP2
KWP6
KWP0
KWP7
KWP1
KWP3
KWP4
KWP5
Timer
Signals shown in Bold-Italics are neither available on the 112-pin nor on the 80-pin oackage option
Module to Port Routing
PWM2
PWM6
PWM0
PWM7
PWM1
PWM3
PWM4
PWM5
PWM
8-Bit PPAGE
PK3
PK0
PK1
PTK
DDRK
PK2
PK4
PK5
PK7
V
RH
V
RL
ATD1
AN2
AN6
AN0
AN7
AN1
AN3
AN4
AN5
PAD03
PAD04
PAD05
PAD06
PAD07
PAD00
PAD01
PAD02
V
DDA
V
SSA
PTAD1
AN10
AN8
AN9
AN11
PAD11
PAD12
PAD13
PAD14
PAD15
PAD08
PAD09
PAD10
PJ6
PJ7
KWJ6
KWJ7
V
DDX
V
SSX
I/O Supply 3-5 V
VDDA
VSSA
Analog Supply 3-5 V
V
DDPLL
V
SSPLL
PLL Supply 2.5 V
Enhanced Multilevel
Interrupt Module
XGATE
Peripheral
V
DD1,2
V
SS1,2
Digital Supply 2.5 V
Signals shown in Bold are not available on the 80-pin package
Allows 4-MByte
Program space
Timer
4-Channel
16-Bit with Prescaler
for Internal Timebases
Single-Wire
Background
Debug Module
V
DDR
Voltage Regulator
V
SSR
V
DD1,2
V
SS1,2
V
REGEN
Clock
and Reset
Generation
Module
CAN4
RXCAN
TXCAN
Co-Processor
AN15
AN14
AN13
AN12
DDRAD1
V
DDA
V
SSA
V
RH
V
RL