Datasheet

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor 379
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
See Section 8.4.2.3, “PWM Period and Duty” for more information.
NOTE
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is zero, the output starts
low and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
To calculate the output duty cycle (high time as a% of period) for a particular channel:
• Polarity = 0 (PPOL x =0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
• Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
For boundary case programming values, please refer to Section 8.4.2.8, “PWM Boundary Cases”.
Read: Anytime
Write: Anytime
8.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.
Read: Anytime
Write: Anytime
76543210
R
Bit 7 6 5 4 3 2 1 Bit 0
W
Reset 11111111
Figure 8-16. PWM Channel Duty Registers (PWMDTYx)
76543210
R
PWMIF PWMIE
0
PWMLVL
0 PWM7IN
PWM7INL PWM7ENA
W PWMRSTRT
Reset 00000000
= Unimplemented or Reserved
Figure 8-17. PWM Shutdown Register (PWMSDN)