Datasheet

Chapter 9 Inter-Integrated Circuit (IICV2) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.21
398 Freescale Semiconductor
9.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
9.3.2.1 IIC Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Register
Name
Bit 7 654321Bit 0
IBAD R
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
W
IBFD R
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
W
IBCR R
IBEN IBIE MS/
SL Tx/Rx TXAK
00
IBSWAI
W
RSTA
IBSR R TCF IAAS IBB
IBAL
0SRW
IBIF
RXAK
W
IBDR R
D7 D6 D5 D4 D3 D2 D1 D0
W
= Unimplemented or Reserved
Figure 9-2. IIC Register Summary
76543210
R
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
0
W
Reset 00000000
= Unimplemented or Reserved
Figure 9-3. IIC Bus Address Register (IBAD)
Table 9-1. IBAD Field Descriptions
Field Description
7:1
ADR[7:1]
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
0
Reserved
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.