Datasheet

Chapter 18 Memory Mapping Control (S12XMMCV3)
MC9S12XDP512 Data Sheet, Rev. 2.21
678 Freescale Semiconductor
Table 18-21 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Figure 18-23. Local to Implemented Global Address Mapping (Without GPAGE)
18.4.2.4 XGATE Memory Map Scheme
18.4.2.4.1 Expansion of the XGATE Local Address Map
The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and
FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the
BDM module . XGATE can access the FLASH in single chip modes, even when the MCU is secured. In
expanded modes, XGATE can not access the FLASH when MCU is secured.
The local address of the XGATE RAM access is translated to the global RAM address range. The XGATE
shares the RAM resource with the CPU and the BDM module . The local address of the XGATE FLASH
access is translated to the global address as shown in Figure 18-24. For the implemented memory spaces
and addresses please refer to Table 1-4 and Table 1-5.
Table 18-21. Global Chip Selects Memory Space
Chip Selects Bottom Address Top Address
CS3 0x00_0800 0x0F_FFFF minus RAMSIZE
1
1
External RPAGE accesses in (NX, EX and ST)
CS2 0x10_0000 0x13_FFFF minus EEPROMSIZE
2
2
External EPAGE accesses in (NX, EX and ST)
CS2
3
3
When ROMHM is set (see ROMHM in Table 18-19) the CS2 is asserted in the space occupied by this
on-chip memory block.
0x14_0000 0x1F_FFFF
CS1 0x20_0000 0x3F_FFFF
CS0
4
4
When the internal NVM is enabled (see ROMON in Section 18.3.2.5, “MMC Control Register (MMCCTL1))
the
CS0 is not asserted in the space occupied by this on-chip memory block.
0x40_0000 0x7F_FFFF minus FLASHSIZE
5
5
External PPAGE accesses in (NX, EX and ST)