Datasheet

23.0.5.6 Port D Data Register (PORTD)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
23.0.5.7 Port C Data Direction Register (DDRC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in
all other modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-8. PORTC Field Descriptions
Field Description
7–0
PC[7:0]
Port C — Port C pins 7–0 can be used as general purpose I/O. If the data direction bits of the associated I/O pins
are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read.
76543210
R
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
W
Reset 00000000
Figure 23-8. Port D Data Register (PORTD)
Table 23-9. PORTD Field Descriptions
Field Description
7–0
PD[7:0]
Port D — Port D pins 7–0. — If the data direction bits of the associated I/O pins are set to logic level “1”, a read
returns the value of the port register, otherwise the buffered pin input state is read.
76543210
R
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
W
Reset 00000000
Figure 23-9. Port C Data Direction Register (DDRC)
Table 23-10. DDRC Field Descriptions
Field Description
7–0
DDRC[7:0]
Data Direction Port C — This register controls the data direction for port C. DDRC determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTC after changing the DDRC register.