Freescale Semiconductor Product Brief 9S12XDFAMPP Rev. 2.16, 27-May-2006 MC9S12XD Family 16-bit Microprocessor Family (covers MC9S12XD64 through MC9S12XDP512 and MC3S12XDT256/MC3S12XDG128) Introduction Targeted at automotive multiplexing applications, the MC9S12XD Family will deliver 32-bit performance with all the advantages and efficiencies of a 16-bit MCU.
Features The MC9S12XD Family will feature an enhanced MSCAN module which, when used in conjunction with XGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retains backwards compatibility with the MSCAN module featured on previous S12 products. Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotive spec SG-Flash with additional integrated EEPROM.
Features XGATE • Programmable, high performance I/O co-processor module — up to 80 MIPS RISC performance • Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states • Performs logical, shifts, arithmetic, and bit operations on data • Enables FullCAN capability when used in conjunction with MSCAN module • Full LIN master or slave capability when used in conjunction with the six integrated LIN SCI modules • Can interrupt the HCS12X CPU signalling transfer compl
Features Clock and Reset Generator (CRG) Non-Multiplexed External Bus (144 Pin package only) Analog-to-Digital Converter (ATD) Enhanced Capture Timer (ECT) • Phase-locked-loop clock frequency multiplier – Reference divider – Automatic bandwidth control mode for low-jitter operation – Automatic frequency lock detector • Fast wakeup from STOP in self clock mode for power saving and immediate program execution • Computer operating properly (COP) watchdog with optional safety window to initialize time
Features Pulse Width Modulator (PWM) Multi-scalable Controller Area Networks (MSCAN) Serial Peripheral Interface (SPI) Serial Communication Interfaces (SCI) • Eight channel x 8-bit or four channel x 16-bit pulse width modulator • Programmable period and duty cycle per channel • Center-aligned or left-aligned outputs • Programmable clock select logic with a wide range of frequencies • Up to five MSCAN modules (see ) • CAN 2.
Features Inter IC Module (IIC) • Up to two IIC modules (see ) • Compatible with I2C Bus standard • Multi-master operation • Software programmable for one of 256 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address identification interrupt • Start and stop signal generation/detection • Repeated start signal generation • Ackn
Features • Ambient temperature range -40°C to 125°C • Temperature options: – -40°C to 85°C – -40°C to 105°C – -40°C to 125°C • Supply voltage 3.15V to 5.5V • Internal voltage regulator providing 2.5 V logic supply – 40 MHz maximum CPU bus frequency in single chip mode – 80 MHz maximum XGATE bus frequency Operating Conditions MC9S12XD Family, Rev. 2.
MC9S12XD Family Block Diagram MC9S12XD Family Block Diagram MC9S12XD Family, Rev. 2.
MC9S12XD Family Block Diagram Digital Supply 2.5V VDD1,2 VSS1,2 CAN0 CAN1 CAN2 CAN3 CAN4 SCI2 PLL Supply 2.
MC9S12XD Family Block Diagram Table 1.
MC9S12XD Family Block Diagram Table 2.
MC9S12XD Family Block Diagram Pinout explanations: • A/D is the number of modules/total number of A/D channels. • I/O is the sum of ports capable to act as digital input or output.
Pin Assignments Pin Assignments Table 3. Port and Peripheral Availability by Package Option Port 144 LQFP 112 LQFP 80 QFP Port AD/ADC Channels 24/24 16/16 8/8 Port A pins 8 8 8 Port B pins 8 8 8 Port C pins 8 0 0 Port D pins 8 0 0 Port E pins incl.
Pin Assignments PH5:4 X PH7:6 IIC1 IIC0 SPI2 SPI1 SPI0 SCI5 SCI4 SCI3 SCI2 SCI1 SCI0 CAN4 CAN3 CAN2 CAN1 CAN0 Table 4. Peripheral–Port Cross Reference(1) O X PP3:0 O X PP7:4 X NOTES: 1. X denotes the reset condition and O denotes a possible rerouting under software control Table 5.
Pin Assignments Table 5.
Pin Assignments Table 5.
Pin Assignments Table 5.
Pin Assignments Table 5. Pin-Out Summary(1) LQFP 144 LQFP 112 QFP 80 136 104 74 PM1 TXCAN0 137 105 75 PM0 RXCAN0 138 106 76 VSSX1 139 107 77 VDDX1 140 108 141 109 142 110 143 111 144 112 Pin 2nd Function 3rd Function 4th Function PK7 ROMCTL EWAIT PP7 KWP7 PWM7 SCK2 PP6 KWP6 PWM6 SS2 79 PP5 KWP5 PWM5 MOSI2 80 PP4 KWP4 PWM4 MISO2 78 5th Function NOTES: 1. Table shows a superset of pin functions.
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ROMCTL/EWAIT VDDX1 VSSX1 PM0/RXCAN0 PM1/TXCAN0 PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ4/KWJ4/SDA1/CS0 PJ5/KWJ5/SCL1/CS2 PJ6/KWJ6/RXCAN4/SDA0 PJ7/KWJ7/TXCAN4/SCL0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 P
MC9S12XD Family 112LQFP Pins shown in BOLD are not available on the 80 QFP package 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VRH VDDA PAD15/AN15 PAD07/AN07 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MC9S12XD Family 80-Pin QFP 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB6 PB7 XCLKS/PE7 MODB/PE6 MODA/PE5 ECLK/PE4 VSSR1 VDDR1 RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST PE3 PE2 IRQ/PE1 XIRQ/PE0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/
Memory Maps Memory Maps $0000 2K Register Space $0800 $0C00 4K Bytes EEPROM 4 * 1K pages accessible through $0800 - $0BFF $1000 $2000 32K Bytes RAM 8 * 4K pages accessible through $1000 - $1FFF $4000 16K Fixed Flash EEPROM External $8000 16K Page Window 32 * 16K Flash EEPROM Pages $C000 16K Fixed Flash EEPROM $FF00 VECTORS VECTORS BDM NORMAL SINGLE CHIP EXPANDED SPECIAL SINGLE CHIP 2K, 4K, 8K or 16K Protected Boot Sector $FFFF Figure 4. MC9S12XD-Family Memory Map1 1.
Memory Maps Global Address $78_0000 DP512/ DT512 DT384 DQ256/ D256 128K 128K 128K DG128/ D128 D64 (PPAGE $E0) $7A_0000 (PPAGE $E8) 128K $7C_0000 (PPAGE $F0) $7E_0000 128K 128K 128K 128K (PPAGE $F8) 128K 128K 64K Shared XGATE/CPU area Not implemented Figure 5. MC9S12XD-Family Flash Configuration1, 2, 3, 4, 5 1. XGATE read access to Flash not possible on DG128/D128 and D64 2. Program Pages available on DT384 are $E0 - $E7 and $F0 - $FF 3.
Mechanical Package Dimensions Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 36 TIPS 144 109 1 108 4X J1 P J1 L M CL B V X G 140X B1 VIEW Y 36 VIEW Y V1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M, N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.
Mechanical Package Dimensions 0.20 T L-M N 4X PIN 1 DENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 AA J V1 57 29 F D 56 0.13 N M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 C VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4.
Mechanical Package Dimensions 41 60 61 B D D S V B P B 0.20 M C A-B L 0.05 D -B- 0.20 M H A-B -A- S S S 40 -A-,-B-,-DDETAIL A DETAIL A 21 80 1 A 0.20 M H A-B S F 20 -DD S 0.05 A-B J S 0.20 M C A-B S D S D M E DETAIL C C -H- -CSEATING PLANE N DATUM PLANE 0.20 M C A-B S D S SECTION B-B VIEW ROTATED 90 ° 0.10 H M G U T DATUM -HPLANE R K W X DETAIL C Q NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3.
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