Datasheet

MC9S12XD Family, Rev. 2.16
6 Freescale Semiconductor
Features
Inter IC Module (IIC)
• Up to two IIC modules (see )
• Compatible with I2C Bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock
frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master
to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
• Acknowledge bit generation/detection
• Bus busy detection
• supports 400 Kbps
Background Debug
(BDM)
•
– Non-intrusive memory access commands
– Supports in-circuit programming of on-chip non-volatile memory
– Supports security
Debugger (XDBG)
– Each can monitor CPU or XGATE busses
– A and C compares 23-bit address bus and 16-bit data bus with
mask register
– Three modes: simple address/data match, inside address range
or outside address range
•
System Protection
• Power-on reset (POR)
• with interrupt or reset
Input/Output
• up to 117 general-purpose input/output (I/O) pins depending on the
package option and 2 input-only pins
• Hysteresis and configurable pullup/pulldown device on all input pins
• Configurable drive strength on all output pins
Package Options
• 144-pin low-profile quad flat-pack (LQFP)
• 112-pin low-profile quad flat-pack (LQFP)
• 80-pin quad flat-pack (QFP)