Datasheet

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
1002 Freescale Semiconductor
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
24.0.5.16 Port T Reduced Drive Register (RDRT)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
24.0.5.17 Port T Pull Device Enable Register (PERT)
Read: Anytime.
Write: Anytime.
Table 24-19. DDRT Field Descriptions
Field Description
7–0
DDRT[7:0]
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTT or PTIT registers, when changing the DDRT register.
76543210
R
RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
Reset 00000000
Figure 24-18. Port T Reduced Drive Register (RDRT)
Table 24-20. RDRT Field Descriptions
Field Description
7–0
RDRT[7:0]
Reduced Drive Port T
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
76543210
R
PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
Reset 00000000
Figure 24-19. Port T Pull Device Enable Register (PERT)