Datasheet

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
320 Freescale Semiconductor
7.3.2.4 Output Compare 7 Data Register (OC7D)
Read or write: Anytime
All bits reset to zero.
76543210
R
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
W
Reset 00000000
Figure 7-6. Output Compare 7 Data Register (OC7D)
Table 7-5. OC7D Field Descriptions
Field Description
7:0
OC7D[7:0]
Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data
register to transfer to the timer port data register depending on the output compare 7 mask register.