Datasheet

Chapter 20 S12X Debug (S12XDBGV3) Module
MC9S12XDP512 Data Sheet, Rev. 2.21
748 Freescale Semiconductor
20.3 Memory Map and Registers
20.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 20-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Table 20-2. External System Pins Associated With S12XDBG
Pin Name Pin Functions Description
TAGHI
(See DUG)
TAGHI When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
TAGLO When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
Unconditional
Tagging Enable
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
Address Name Bit 7 6 5 4321Bit 0
0x0020 DBGC1
R
ARM
0
XGSBPE BDM DBGBRK COMRV
W TRIG
0x0021 DBGSR
R TBF EXTF 0 0 0 SSF2 SSF1 SSF0
W
0x0022 DBGTCR
R
TSOURCE TRANGE TRCMOD TALIGN
W
0x0023 DBGC2
R0000
CDCM ABCM
W
0x0024 DBGTBH
R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
0x0025 DBGTBL
R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0026 DBGCNT
R 0 CNT
W
0x0027 DBGSCRX
R0000
SC3 SC2 SC1 SC0
W
0x0027 DBGMFR
R 0 0 0 0 MC3 MC2 MC1 MC0
W
0x0028
1
DBGXCTL
(COMPA/C)
R0
NDB TAG BRK RW RWE SRC COMPE
W
0x0028
2
DBGXCTL
(COMPB/D)
R
SZE SZ TAG BRK RW RWE SRC COMPE
W
0x0029 DBGXAH
R0
Bit 22 21 20 19 18 17 Bit 16
W
Figure 20-2. Quick Reference to S12XDBG Registers