Datasheet

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
970 Freescale Semiconductor
Table 23-70 lists the pin functions in relationship with the different operating modes. If two entries per pin
are displayed, a ‘mux’ indicates time-multiplexing between the two functions and an ‘or’ means that a
configuration bit exists which can be altered after reset to select the respective function (displayed in
italics). Refer to S12X_EBI section for details.
Table 23-70. Expanded Bus Pin Functions versus Operating Modes
Pin
Single-Chip Modes Expanded Modes
Normal Single-
Chip
Special Single-
Chip
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
PK7 GPIO GPIO GPIO
or
EWAIT
GPIO GPIO
or
EWAIT
GPIO
PK[6:4] GPIO GPIO ADDR[22:20]
or
GPIO
ADDR[22:20]
mux
ACC[2:0]
ADDR[22:20]
mux
ACC[2:0]
ADDR[22:20]
PK[3:0] GPIO GPIO ADDR[19:16]
or
GPIO
ADDR[19:16]
mux
IQSTAT[3:0]
ADDR[19:16]
mux
IQSTAT[3:0]
ADDR[19:16]
PA[7:0] GPIO GPIO ADDR[15:8]
or
GPIO
ADDR[15:8]
mux
IVD[15:8]
ADDR[15:8]
mux
IVD[15:8]
ADDR[15:8]
PB[7:1] GPIO GPIO ADDR[7:1]
or
GPIO
ADDR[7:1]
mux
IVD[7:1]
ADDR[7:1]
mux
IVD[7:1]
ADDR[7:1]
PB0 GPIO GPIO UDS
or
GPIO
ADDR0
mux
IVD0
ADDR0
mux
IVD0
ADDR0
PC[7:0] GPIO GPIO DATA[15:8]
or
GPIO
DATA[15:8] DATA[15:8] DATA[15:8]
or
GPIO
PD[7:0] GPIO GPIO DATA[7:0] DATA[7:0] DATA[7:0] DATA[7:0]
PE7 GPIO
or
ECLKX2
GPIO
or
ECLKX2
GPIO
or
ECLKX2
ECLKX2 ECLKX2 GPIO
or
ECLKX2
PE6 GPIO GPIO GPIO TAGHI TAGHI GPIO
PE5 GPIO GPIO RE TAGLO TAGLO GPIO
PE4 GPIO
or
ECLK
ECLK
or
GPIO
ECLK
or
GPIO
ECLK ECLK ECLK
or
GPIO
PE3 GPIO GPIO
LDS
or
GPIO
LSTRB LSTRB LSTRB
PE2 GPIO GPIO
WE R/WR/WR/W
PJ5 GPIO GPIO GPIO
or
CS2
GPIO GPIO
or
CS2
GPIO
or
CS2
PJ4 GPIO GPIO GPIO
or
CS0
(1)
GPIO GPIO
or
CS0
(1)
GPIO
or
CS0