Datasheet

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor 1189

NOTE

Vector addresses and their relative interrupt priority are determined at the

MCU level.

28.8.1 Description of Flash Interrupt Operation

The logic used for generating interrupts is shown in Figure 28-32.

The Flash module uses the CBEIF and CCIF ﬂags in combination with the CBIE and CCIE enable bits to

generate the Flash command interrupt request.

Figure 28-32. Flash Interrupt Implementation

For a detailed description of the register bits, refer to Section 28.3.2.4, “Flash Conﬁguration Register

(FCNFG)” and Section 28.3.2.6, “Flash Status Register (FSTAT)” .

Table 28-19. Flash Interrupt Sources

Interrupt Source Interrupt Flag Local Enable Global (CCR) Mask

Flash Address, Data and Command Buffers empty CBEIF

(FSTAT register)

CBEIE

(FCNFG register)

I Bit

All Flash commands completed CCIF

(FSTAT register)

CCIE

(FCNFG register)

I Bit

Flash Command Interrupt Request

CBEIE

CBEIF

CCIE

CCIF