Datasheet

Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor 543
13.3 Memory Map and Register Definition
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7 654321Bit 0
PITCFLMT R
PITE PITSWAI PITFRZ
00000
W
PFLMT1 PFLMT0
PITFLT R 0 0000000
W
PFLT3 PFLT2 PFLT1 PFLT0
PITCE R 0 0 0 0
PCE3 PCE2 PCE1 PCE0
W
PITMUX R 0 0 0 0
PMUX3 PMUX2 PMUX1 PMUX0
W
PITINTE R 0 0 0 0
PINTE3 PINTE2 PINTE1 PINTE0
W
PITTF R 0 0 0 0
PTF3 PTF2 PTF1 PTF0
W
PITMTLD0 R
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
W
PITMTLD1 R
PMTLD7 PMTLD6 PMTLD5 PMTLD4 PMTLD3 PMTLD2 PMTLD1 PMTLD0
W
PITLD0 (High) R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8
W
PITLD0 (Low) R
PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
W
PITCNT0 (High) R
PCNT15 PCNT14 PCNT13 PCNT12 PCNT11 PCNT10 PCNT9 PCNT8
W
PITCNT0 (Low) R
PCNT7 PCNT6 PCNT5 PCNT4 PCNT3 PCNT2 PCNT1 PCNT0
W
PITLD1 (High) R
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8
W
= Unimplemented or Reserved
Figure 13-2. PIT Register Summary (Sheet 1 of 2)