Datasheet

23.0.5.53 Port H Interrupt Flag Register (PIFH)

Read: Anytime.

Write: Anytime.

Each flag is set by an active edge on the associated input pin. This could be a rising or a falling

edge based on the state of the PPSH register. To clear this flag, write logic level “1” to the

corresponding bit in the PIFH register. Writing a “0” has no effect.

Table 23-49. PIEH Field Descriptions

Field Description

7–0

PIEH[7:0]

Interrupt Enable Port H

0 Interrupt is disabled (interrupt ﬂag masked).

1 Interrupt is enabled.

76543210

PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0

Reset 00000000

Figure 23-55. Port H Interrupt Flag Register (PIFH)

Table 23-50. PIFH Field Descriptions

Field Description

7–0

PIFH[7:0]

Interrupt Flags Port H

0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.