Datasheet

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
MC9S12XDP512 Data Sheet, Rev. 2.21
1196 Freescale Semiconductor
29.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
29.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
RESERVED1 R 0 0000000
W
RESERVED2 R 0 0000000
W
RESERVED3 R 0 0000000
W
RESERVED4 R 0 0000000
W
76543210
R FDIVLD
PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 29-4. Flash Clock Divider Register (FCLKDIV)
Table 29-2. FCLKDIV Field Descriptions
Field Description
7
FDIVLD
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
6
PRDIV8
Enable Prescalar by 8
.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5:0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 29.4.1.1, “Writing the
FCLKDIV Register” for more information.
Register
Name
Bit 7 654321Bit 0
Figure 29-3. FTX128K1 Register Summary (continued)