Datasheet

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
164 Freescale Semiconductor
ATDDR3L 10-BIT
BIT 1
U
BIT 0
U
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
W
ATDDR4H 10-BIT
BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR4L 10-BIT
BIT 1
U
BIT 0
U
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
W
ATDD45H 10-BIT
BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDD45L 10-BIT
BIT 1
U
BIT 0
U
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
W
ATDD46H 10-BIT
BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDDR6L 10-BIT
BIT 1
U
BIT 0
U
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
W
ATDD47H 10-BIT
BIT 9 MSB
BIT 7 MSB
BIT 8
BIT 6
BIT 7
BIT 5
BIT 6
BIT 4
BIT 5
BIT 3
BIT 4
BIT 2
BIT 3
BIT 1
BIT 2
BIT 0
8-BIT
W
ATDD47L 10-BIT
BIT 1
U
BIT 0
U
0
0
0
0
0
0
0
0
0
0
0
0
8-BIT
W
Right Justified Result Data
Note: The read portion of the right justified result data registers has been divided to show the bit position when reading 10-bit
and 8-bit conversion data. For more detailed information refer to Section 5.3.2.13, “ATD Conversion Result Registers
(ATDDRx)”.
ATDDR0H 10-BIT
0
0
0
0
0
0
0
0
0
0
0
0
BIT 9 MSB
0
BIT 8
0
8-BIT
W
ATDDR0L 10-BIT
BIT 7
BIT 7 MSB
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
BIT 0
BIT 0
8-BIT
W
Register
Name
Bit 7 654321Bit 0
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 3 of 5)