Datasheet

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
350 Freescale Semiconductor
Read: Anytime
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding
IOSx bits in TIOS should be cleared (see Section 7.4.1.1, “IC Channels”).
7.4 Functional Description
This section provides a complete functional description of the ECT block, detailing the operation of the
design from the end user perspective in a number of subsections.
15 14 13 12 11 10 9 8
R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
W
Reset 00000000
= Unimplemented or Reserved
Figure 7-63. Timer Input Capture Holding Register 3 High (TC3H)
76543210
R TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 7-64. Timer Input Capture Holding Register 3 Low (TC3H)