Datasheet

Chapter 20 S12X Debug (S12XDBGV3) Module
MC9S12XDP512 Data Sheet, Rev. 2.21
746 Freescale Semiconductor
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
20.1.3 Features
Four comparators (A, B, C, and D)
Comparators A and C compare the full address bus and full 16-bit data bus
Comparators A and C feature a data bus mask register
Comparators B and D compare the full address bus only
Each comparator can be configured to monitor either S12XCPU or XGATE buses
Each comparator features control of R/W and byte/word access cycles
Comparisons can be used as triggers for the state sequencer
Three comparator modes
Simple address/data comparator match mode
Inside address range mode, Addmin Address Addmax
Outside address range match mode, Address < Addmin or Address > Addmax
Two types of triggers
Tagged — This triggers just before a specific instruction begins execution
Force — This triggers on the first instruction boundary after a match occurs.
Three types of breakpoints
S12XCPU breakpoint entering BDM on breakpoint (BDM)
S12XCPU breakpoint executing SWI on breakpoint (SWI)
XGATE breakpoint
Three trigger modes independent of comparators
External instruction tagging (associated with S12XCPU instructions only)
XGATE S/W breakpoint request
TRIG Immediate software trigger
Four trace modes
Normal: change of flow (COF) PC information is stored (see Section 20.4.5.2.1) for change of
flow definition.
Loop1: same as Normal but inhibits consecutive duplicate source address entries
Detail: address and data for all cycles except free cycles and opcode fetches are stored
Pure PC: All program counter addresses are stored.
4-stage state sequencer for trace buffer control
Tracing session trigger linked to Final State of state sequencer
Begin, End, and Mid alignment of tracing to trigger
20.1.4 Modes of Operation
The S12XDBG module can be used in all MCU functional modes.