Datasheet

This register is associated with AD0 pins PAD[23:10]. These pins can also be used as general
purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
23.0.5.63 Port AD0 Data Direction Register 1 (DDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[07:00] as either input or output.
23.0.5.64 Port AD0 Reduced Drive Register 1 (RDR1AD0)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each output pin PAD[07:00] as either full or reduced.
If the port is used as input this bit is ignored.
76543210
R
DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
W
Reset 00000000
Figure 23-65. Port AD0 Data Direction Register 1 (DDR1AD0)
Table 23-58. DDR1AD0 Field Descriptions
Field Description
7–0
DDR1AD0[7:0]
Data Direction Port AD0 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD01 register, when changing the DDR1AD0 register.
Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to
be set to logic level “1”.
76543210
R
RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00
W
Reset 00000000
Figure 23-66. Port AD0 Reduced Drive Register 1 (RDR1AD0)