Datasheet

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.21
442 Freescale Semiconductor
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 10-20. CANIDAR0–CANIDAR3 Register Field Descriptions
Field Description
7:0
AC[7:0]
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Module Base + 0x0018 (CANIDAR4)
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
76543210
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 00000000
76543210
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 00000000
76543210
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 00000000
76543210
R
AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0
W
Reset 00000000
Figure 10-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7