Datasheet

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
994 Freescale Semiconductor
24.0.5.4 Port B Data Direction Register (DDRB)
Read: Anytime.
Write: Anytime.
24.0.5.5 Port E Data Register (PORTE)
Read: Anytime.
Write: Anytime.
76543210
R
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
W
Reset 00000000
Figure 24-6. Port B Data Direction Register (DDRB)
Table 24-7. DDRB Field Descriptions
Field Description
7–0
DDRB[7:0]
Data Direction Port B — This register controls the data direction for port B. DDRB determines whether each pin
is an input or output. A logic level “1” causes the associated port pin to be an output and a logic level “0” causes
the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTB after changing the DDRB register.
76543210
R
PE7 PE6 PE5 PE4 PE3 PE2
PE1 PE0
W
Alt.
Func.
XCLKS
or
ECLKX2
MODB MODA ECLK EROMCTL
IRQ XIRQ
Reset 000000—
1
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
—
1
= Unimplemented or Reserved
Figure 24-7. Port E Data Register (PORTE)