Datasheet

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor 1163
28.3.2.7 Flash Command Register (FCMD)
The FCMD register is the Flash command register.
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
28.3.2.8 Flash Control Register (FCTL)
The FCTL register is the Flash control register.
All bits in the FCTL register are readable but are not writable.
The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during
the reset sequence, indicated by F in Figure 28-15.
76543210
R0
CMDB
W
Reset 11000000
= Unimplemented or Reserved
Figure 28-14. Flash Command Register (FCMD)
Table 28-15. FCMD Field Descriptions
Field Description
6:0
CMDB[6:0]
Flash Command — Valid Flash commands are shown in Table 28-16. Writing any command other than those
listed in Table 28-16 sets the ACCERR flag in the FSTAT register.
Table 28-16. Valid Flash Command List
CMDB[6:0] NVM Command
0x05 Erase Verify
0x06 Data Compress
0x20 Word Program
0x40 Sector Erase
0x41 Mass Erase
0x47 Sector Erase Abort
76543210
R 0 NV6 NV5 NV4 NV3 NV2 NV1 NV0
W
Reset 0 F F FFFFF
= Unimplemented or Reserved
Figure 28-15. Flash Control Register (FCTL)