Datasheet

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
MC9S12XDP512 Data Sheet, Rev. 2.21
1198 Freescale Semiconductor
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
29.3.2.4 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not
writable in normal mode. KEYACC is only writable if KEYEN (see Section 29.3.2.2, “Flash Security
Register (FSEC)” is set to the enabled state.
76543210
R0
MRDS
00000
W
Reset 00000000
= Unimplemented or Reserved
Figure 29-6. Flash Test Mode Register (FTSTMOD)
Table 29-6. FTSTMOD Field Descriptions
Field Description
6:5
MRDS[1:0]
Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
array as shown in Table 29-7.
Table 29-7. FTSTMOD Margin Read Settings
MRDS[1:0] Margin Read Setting
00 Normal
01 Program Margin
1
1 Flash array reads will be sensitive to program margin.
10 Erase Margin
2
2 Flash array reads will be sensitive to erase margin.
11 Normal
76543210
R
CBEIE CCIE KEYACC
Undefined 0000
W
Reset 0 0 0 Undefined 0000
= Unimplemented or Reserved
Figure 29-7. Flash Configuration Register (FCNFG)