Datasheet

Chapter 6 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
198 Freescale Semiconductor
6.3.1.8 XGATE Program Counter Register (XGPC)
The XGPC register (Figure 6-10) provides access to the RISC core’s program counter.
Read: In debug mode if unsecured
Write: In debug mode if unsecured
6.3.1.9 XGATE Register 1 (XGR1)
The XGR1 register (Figure 6-12) provides access to the RISC core’s register 1.
Read: In debug mode if unsecured
Write: In debug mode if unsecured
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
XGPC
W
Reset 0 0 0 0000000000000
Figure 6-10. XGATE Program Counter Register (XGPC)
Figure 6-11.
Table 6-8. XGPC Field Descriptions
Field Description
15–0
XGPC[15:0]
Program Counter — The RISC core’s program counter
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
XGR1
W
Reset 0 0 0 0000000000000
Figure 6-12. XGATE Register 1 (XGR1)
Table 6-9. XGR1 Field Descriptions
Field Description
15–0
XGR1[15:0]
XGATE Register 1 — The RISC core’s register 1