Datasheet

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
314 Freescale Semiconductor
7.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7 654321Bit 0
TIOS R
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
W
CFORC R 00000000
W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
OC7M R
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
W
OC7D R
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
W
TCNT (High) R
TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
W
TCNT (Low) R
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
W
TSCR1 R
TEN TSWAI TSFRZ TFFCA PRNT
000
W
TTOF R
TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0
W
TCTL1 R
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
W
TCTL2 R
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
W
TCTL3 R
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
W
TCTL4 R
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
W
TIE R
C7I C6I C5I C4I C3I C2I C1I C0I
W
= Unimplemented or Reserved
Figure 7-2. ECT Register Summary (Sheet 1 of 5)