Datasheet

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.21
430 Freescale Semiconductor
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 10-7 and Table 10-8).
Eqn. 10-1
10.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Table 10-7. Time Segment 2 Values
TSEG22 TSEG21 TSEG20 Time Segment 2
0 0 0 1 Tq clock cycle
1
1
This setting is not valid. Please refer to Table 10-35 for valid settings.
0 0 1 2 Tq clock cycles
::: :
1 1 0 7 Tq clock cycles
1 1 1 8 Tq clock cycles
Table 10-8. Time Segment 1 Values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1
0 0 0 0 1 Tq clock cycle
1
1
This setting is not valid. Please refer to Table 10-35 for valid settings.
0 0 0 1 2 Tq clock cycles
1
0 0 1 0 3 Tq clock cycles
1
0 0 1 1 4 Tq clock cycles
:::: :
1 1 1 0 15 Tq clock cycles
1 1 1 1 16 Tq clock cycles
76543210
R
WUPIF CSCIF
RSTAT1 RSTAT0 TSTAT1 TSTAT0
OVRIF RXF
W
Reset: 00000000
= Unimplemented
Figure 10-8. MSCAN Receiver Flag Register (CANRFLG)
Bit Time
Prescaler value()
f
CANCLK
------------------------------------------------------
1 TimeSegment1 TimeSegment2++()•=