Datasheet

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
928 Freescale Semiconductor
23.0.5.13 ECLK Control Register (ECLKCTL)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
76543210
R
NECLK NCLKX2
0000
EDIV1 EDIV0
W
Reset
1
1. Reset values in emulation modes are identical to those of the target mode.
Mode
Dependent
1000000Mode
SS
01000000
Special
Single-Chip
ES
11000000
Emulation
Single-Chip
ST
01000000
Special
Test
EX
01000000
Emulation
Expanded
NS
11000000
Normal
Single-Chip
NX
01000000
Normal
Expanded
= Unimplemented or Reserved
Figure 23-15. ECLK Control Register (ECLKCTL)
Table 23-16. ECLKCTL Field Descriptions
Field Description
7
NECLK
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled