Datasheet

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
958 Freescale Semiconductor
23.0.5.65 Port AD0 Pull Up Enable Register 1 (PER1AD0)
Read: Anytime.
Write: Anytime.
This register activates a pull-up device on the respective pin PAD[07:00] if the port is used as input. This
bit has no effect if the port is used as output. Out of reset no pull device is enabled.
23.0.5.66 Port AD1 Data Register 0 (PT0AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[23:16]. These pins can also be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
Table 23-59. RDR1AD0 Field Descriptions
Field Description
7–0
RDR1AD0[7:0]
Reduced Drive Port AD0 Register 1
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
76543210
R
PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00
W
Reset 00000000
Figure 23-67. Port AD0 Pull Up Enable Register 1 (PER1AD0)
Table 23-60. PER1AD0 Field Descriptions
Field Description
7–0
PER1AD0[7:0]
Pull Device Enable Port AD0 Register 1
0 Pull-up device is disabled.
1 Pull-up device is enabled.
76543210
R
W
PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116
Reset 00000000
Figure 23-68. Port AD1 Data Register 0 (PT0AD1)