Datasheet

Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.21
1276 Freescale Semiconductor
In Table A-26 the timing characteristics for master mode are listed.
Figure A-8. Derating of maximum f
SCK
to f
bus
ratio in Master Mode
In Master Mode the allowed maximum f
SCK
to f
bus
ratio (= minimum Baud Rate Divisor, pls. see
SPI Section) derates with increasing f
bus.
A.7.2 Slave Mode
In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
Table A-26. SPI Master Mode Timing Characteristics
Num C Characteristic Symbol Min Typ Max Unit
1 D SCK frequency f
sck
1/2048 — 1/2f
bus
1 D SCK period t
sck
2 — 2048 t
bus
2 D Enable lead time t
lead
— 1/2 — t
sck
3 D Enable lag time t
lag
— 1/2 — t
sck
4 D Clock (SCK) high or low time t
wsck
— 1/2 — t
sck
5 D Data setup time (inputs) t
su
8——ns
6 D Data hold time (inputs) t
hi
8——ns
9 D Data valid after SCK edge t
vsck
— — 15 ns
10 D Data valid after
SS fall (CPHA = 0) t
vss
— — 15 ns
11 D Data hold time (outputs) t
ho
0——ns
12 D Rise and fall time inputs t
rfi
—— 8 ns
13 D Rise and fall time outputs t
rfo
—— 8 ns
1/2
1/4
f
SCK
/f
bus
f
bus
[MHz]
10 20 30 40
15 25 355