Datasheet

23.0.5.17 Port T Data Register (PTT)
Read: Anytime.
Write: Anytime.
23.0.5.18 Port T Input Register (PTIT)
Read: Anytime.
Write: Never, writes to this register have no effect.
Table 23-20. DDRK Field Descriptions
Field Description
7–0
DDRK[7:0]
Data Direction Port K
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTK after changing the DDRK register.
76543210
R
PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
ECT IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
Reset 00000000
Figure 23-19. Port T Data Register (PTT)
Table 23-21. PTT Field Descriptions
Field Description
7–0
PTT[7:0]
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset
1
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
————————
= Unimplemented or Reserved
Figure 23-20. Port T Input Register (PTIT)