Datasheet
Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
990 Freescale Semiconductor
PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
DDRP R
DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
RDRP R
RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
W
PERP R
PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
PPSP R
PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
PIEP R
PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
PIFP R
PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
PTH R
PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
W
DDRH R
DDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
W
RDRH R
RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
W
PERH R
PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
W
PPSH R
PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
W
PIEH R
PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
W
PIFH R
PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
Register
Name
Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 24-2. PIM Register Summary (Sheet 5 of 7)