Datasheet

24.0.5.14 Port T Input Register (PTIT)
Read: Anytime.
Write: Never, writes to this register have no effect.
24.0.5.15 Port T Data Direction Register (DDRT)
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output
compare. In this case the data direction bits will not change.
Table 24-17. PTT Field Descriptions
Field Description
7–0
PTT[7:0]
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset
1
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
————————
= Unimplemented or Reserved
Figure 24-16. Port T Input Register (PTIT)
Table 24-18. PTIT Field Descriptions
Field Description
7–0
PTIT[7:0]
Port T Input — This register always reads back the buffered state of the associated pins. This can also be used
to detect overload or short circuit conditions on output pins.
76543210
R
DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 00000000
Figure 24-17. Port T Data Direction Register (DDRT)